Fast switching of information, be it samples of analog signals or alphanumeric data, is an important task in a communication network. The network nodes in which lines or transmission links from various directions are interconnected for exchanging information between them are often the cause of delay in the transmission. If much traffic is concentrated in a node, and if in particular most of the traffic passes through only few of the links, increased delays or even loss of information are often encountered. It is therefore desirable to have switching nodes which allow fast routing and are at least partially non-blocking.
In EP 312628 is described a switching apparatus for interconnecting a plurality of incoming and outgoing transmission links of a communication network, or for exchanging data between incoming and outgoing computer- and workstation connection links. Furthermore, known packet formats are described.
An overview over prior art switching technology is given on the Internet page www.zurich.ibm.com/Technology/ATM/SWOCPWP, wherein an introduction into the PRIZMA Chip is illustrated. Another source for information about this topic is the publication "A flexible shared-buffer switch for ATM at Gbit/s rates" by W. E. Denzel, A. P. J. Engbersen, I. Iliadis in Computer Networks and ISDN Systems, (0169-7552194), Elsevier Science B.V., Vol. 27, No. 4, pp. 611-624.
The PRIZMA chip has 16 input ports and 16 output ports which provide a port speed of 300-400 Mbit/s. The switch's principle is first to route incoming packets through a fully parallel I/O routing tree and then to queue the routed packets in an output buffer. In addition to this the chip uses a separation between data (payload) and control (header) flow. Only the payloads are stored in a dynamically shared output buffering storage. With this architecture head-of-the-line-queueing is avoided. The PRIZMA chip has a scaleable architecture and hence offers multiple expansion capabilities with which the port speed, the number of ports and the data throughput can be increased. These expansions can be realized based on a modular use of the PRIZMA. Also single-stage or multi-stage switch fabrics can be constructed in a modular way.
The PRIZMA chip is especially suited for broadband telecommunications, based on ATM, i.e. the Asynchronous Transfer Mode. However, the concept is not restricted to ATM-oriented architectural environments. ATM is based on short, fixed-length packets, often called cells and is supposed to be applied as the integrated switching and transmission standard for the future public Broadband Integrated Services Digital Network (BISDN). PRIZMA's topology and queuing arrangement for contention resolution employs a high degree of parallelism. The routing function is performed in a distributed way at the hardware level, referred to as self-routing. ATM packets are classified into several packet types, particularly packet types with different payload sizes, and the PRIZMA chip is dedicated to handle packets with a payload up to 64 bytes. However also packet payloads with 12, 16, 32 or 48 bytes are often to be transported.
A typical dimension of the shared memory section in PRIZMA contains 128 storage cells with a cell length of 64 bytes for storing at maximum 128 packets, independent from their size. When the PRIZMA chip is used in a speed-expansion mode, whereby four chips operate in parallel and each chip receives a quarter of the payload, automatically smaller payloads occur, which means that a considerable amount of memory is not used.
Furthermore, the write and read processes of payloads in the memory are synchronous, which means that asynchronously arriving packets have to wait until the common write pointer for all storage cells is passing the first byte for all storage cells. This can lead to additional latency of up to 63 clock cycles.